erformance Static CMOS Technology
150 MHz (6.67-ns Cycle Time)
Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design
JTAG Boundary Scan Support(1)
High-Performance 32-Bit CPU (TMS320C28x)
16 x 16 and 32 x 32 MAC Operations
16 x 16 Dual MAC
Harvard Bus Architecture
Atomic Operations
Fast Interrupt Response and Processing
Unified Memory Programming Model
4M Linear Program/Data Addre